This invention relates to field-effect transistors, and more particularly to a Schottky-barrier-gate field-effect transistor including field oxide.
In the formation of a Schottky-barrier-gate field-effect transistor including a field oxide, serious problems have been presented. Generally, it has been found necessary to use a first mask for field ion implantation, and a second, smaller mask for field oxide growth, to ensure that the region of field ion implantation is spaced from the conductive gate portion which contacts the semiconductor body. This is so because contact of the gate with the field ion implantation region would provide shorting out of the device.
The necessity for using two separate masking techniques results in alignment problems of the oxide and field ion implantation regions. Use of the same mask for field ion implantation and also for growth of field oxide would result in the above described undesirable contact between the field ion implantation region and the conductive gate.
For these reasons, Schottky-barrier-gate field-effect transistors are generally not formed with field oxide, as are, for example, metal-oxide-semiconductor transistors. Rather the gate of the typical Schottky-barrier-gate field-effect transistor is a large, continuous member completely surrounding the drain and in turn being substantially surrounded by the source. (See, for example, "Femto Joule Logic Circuit With Enhancement-Type Schottky Barrier Gate FET," by Muta et al., IEEE Transactions on Electron Devices, Vol. ED-23, No. 9, September 1976, pages 1023-1027. See also "Si and GaAs 0.5 .mu.m-gate Schottky-Barrier Field-Effect Transistors," W. Baechtold et al., Electronics Letters, May 17, 1973, Vol. 9, No. 10, pages 232-234, and "Microwave Silicon Schottky-Barrier Field-Effect Transistor," K. E. Drangeid et al., Electronics Letters, August 23, 1968, Vol 4, No. 17, pages 362-363.)
Obviously, such transistors are relatively inefficient in the use of wafer area.